1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to the structure of a scan driver IC to be incorporated into the liquid crystal display device.
2. Discussion of the Related Art
The cathode ray tube (CRT) is the most widely used display device in a television set or a computer monitor, because the CRT can easily reproduce full color images at a high response speed. However, the CRT is bulky, heavy, and requires a high supply of power, making portable implementations difficult. Research and development in recent years has led to display alternatives to overcome these disadvantages of the CRT. Among these alternatives is the liquid crystal display (LCD).
The LCD can be applied to a thin television set, such as those used for mounting on the wall. This is because the LCD does not employ an electron gun as the CRT does. Furthermore, the LCD can be applied to a portable display device such as a note-book computer, because the power consumption of an LCD is low enough to be driven by a battery.
As shown in FIG. 1, the LCD device includes a liquid crystal panel, a scan driver 15 and a data driver 14. The liquid crystal panel comprises a matrix array of a plurality of scan lines 10 and a plurality of data lines 11. At the intersections of the scan lines 10 and data lines 11, thin film transistors, such as thin film transistor (TFT) 12 are formed. At a rectangular area surrounded by two neighboring scan lines and two neighboring data lines, a pixel electrode is formed to be connected to the TFT 12. The scan driver 15 applies scan signals, which are either ON or OFF signals, to the gates of the respective TFT's 12 through the scan lines sequentially. The data driver 14 applies data signals to the data lines in order to send the image data to the pixel electrodes through the TFT's driven by the scan signal.
According to the conventional art, as shown FIG. 2, the scan driver 15 includes a plurality of odd row selectors and a plurality of even row selectors connected in series. The odd row selector includes an M2 transistor having a gate connected to an SIn terminal, to which a shift input signal is applied. The M2 transistor also has a drain connected to a first common voltage Vss1. An M1 transistor has a gate connected to an S1o terminal, to which a first clock signal is applied. The M1 transistor also has a source connected to a high voltage signal Vcc and a drain connected to the source of the M2 transistor. An M4 transistor has a gate connected to the SIn terminal and a source connected to an S2o terminal, to which a second clock signal is applied. The M3, M5 and M7 transistors each have gates connected to a node a2, which connects the drain of the M1 transistor and the source of the M2 transistor. An M6 transistor has a gate connected to the drain of the M4 transistor and a source connected to a third clock signal S30. An M11 transistor has a gate connected to the SIn terminal and a source connected to the Vss1 common voltage. An M9 transistor has a gate connected to a fourth clock signal S4, which has twice the cycle of S1o. The M9 transistor also has a source connected to the next scan line. An M10 transistor has a gate connected to the drain of the M9 transistor and a source connected to the drain of the M11 transistor An M8 transistor has a gate connected to a node d2, which is connected to the source of the M10 transistor and the drain of the M11 transistor. The M8 transistor also has a drain connected to the source of the M7 and the drain of the M6, as well as a source connected to the drain of the M7 and a second common voltage Vss.
The even selector includes an M2 transistor having a gate connected to an SIn+1 terminal, to which a shift input signal is applied. The M2 transistor also has a drain connected to the first common voltage Vss1. An M1 transistor has a gate connected to an S1e terminal, to which a first clock signal is applied. The M1 transistor also has a source connected to the high signal voltage Vcc, as well as a drain connected to the source of the M2 transistor. An M4 transistor has a gate connected to the SIn+1 terminal and a source connected to an S2e terminal, to which a second clock signal is applied. The M3, M5 and M7 transistors each have gates connected to a node a3, which connects the drain of the M1 transistor and the source of the M2 transistor. An M6 transistor has a gate connected to the drain of the M4 transistor and a source connected to a third clock signal S3c. An M11 transistor has a gate connected to the SIn+1 terminal and a source connected to the common voltage Vss1. An M9 transistor has a gate connected to a fourth clock signal S4 which has twice the cycle of the S1e clock signal. The M9 transistor also has a source connected to a next row (scan line). An M10 transistor has a gate connected to the drain of the M9 transistor and a source connected to the drain of the M11 transistor. An M8 transistor has a gate connected to a node d3, which connects the source of the M10 transistor and the drain of the M11 transistor. The M8 transistor also has a drain connected to the source of the M7 transistor and the drain of the M6 transistor. The M8 transistor has a source connected to the drain of the M7 transistor and the second common voltage Vss.
Here, the three clock signals applied to the odd row selector, S1o, S2o and S3o, and the three clock signals applied to the even row selector, S1e, S2e and S3e, have twice the cycle of the horizontal sync signal. The clock signals applied to the odd row selector have a "HIGH" pulse when the clock signals applied to the even row selector have a "LOW" pulse and vice versa. Moreover, the clock signal S4 has the same cycle as the horizontal sync signal. Because of this, the odd row selector sends the scan signal generated by the S1o, S2o, S3o and SIn signals to the scan line connected thereto. The even row selector sends the scan signal generated by the S1e, S2e, S3e and SIn+1 signals to the scan line connected thereto. When the nth row selector sends the scan signal to the nth scan line, the scan signal is sent to the next row selector as a shift signal. If the nth row selector is an odd row selector, the shift signal is sent to the SIn+1 terminal of the next (even) row signal. An initial shift signal is applied to the first row selector.
The operation of the scan driver will be explained with reference to the circuit diagram FIG. 2 and the clock signal diagram FIG. 3. Assume that the first row selector shown in FIG. 2 is an odd row selector, and the initial shift signal, in a "HIGH" state for selecting the first scan line, is applied to the SIn terminal. As a result, the M2 and M4 transistors are turned on at time t2. When the S1o and S2o terminals are in a "LOW" state, the sources and drains of the M2 and M4 transistors are also not provided with any "HIGH" signal. In this condition, the M3, M5 and M7 transistors are not turned on. Since the M4 transistor is not turned on, neither is the M6 transistor.
After a "HIGH" signal is applied to SIn, if the clock signal S1o generated by the horizontal sync signal is "HIGH", then the M1 transistor is turned on at time t3 (FIG. 3). Then, the M3, M5 and M7 transistors are all turned on. These transistors are connected to the node a2 connecting the M1 and M2 transistors. However, the M5 transistor is not supplied with a "HIGH" signal, because the M4 transistor is not provided with a "HIGH" signal (S2o is "LOW"). Moreover, the M7 transistor is not supplied with a "HIGH" voltage, because the M6 transistor is not turned on. Before the S1o clock signal changes to "LOW", the S2o clock signal becomes "HIGH" at time t4. So the M6 transistor is turned on by the signal of the M4 transistor through node b1 at time t4. At that time, the S2o voltage through the MS transistor passes the M11 transistor turned on by the SIn signal and turns on the M8 transistor. When the S1o signal becomes "LOW" at time t5, the M1 transistor is turned off and the M5 and M7 transistors, of which gates are connected to the node a2, are also turned off at time t5. When S1o is "LOW" and S2o is "HIGH", S1o becomes "HIGH" at time t6. At that time, the M6 transistor is turned on by the clock signal S2o, and the clock signal S2o is applied to the first scan line connected to the Rn terminal.
At the same time, the S3o clock signal is applied to the Rn+1 of the next (second) row selector for the terminal Rn+1 as a shift signal. When the S1e of the second row selector becomes "HIGH" at time t7, the SIn becomes "LOW". At that time, the M2, M4 and M11 transistors in the first row selector are turned off and the second row selector starts working in a similar manner to the first row selector, as described above.
In manufacturing a conventional LCD device, the liquid crystal panel and the driving ICs are separately manufactured and assembled using a lead wire of lead film. In recent years, there is a need for manufacturing the driving ICs directly on the liquid crystal panel. However, the conventional structure of the driving circuit is so complicated and includes so many lead lines as not to allow manufacturing of the driving circuit directly on the liquid crystal panel. Moreover, the clock signal's converting to a "HIGH" signal lags behind the horizontal sync signal's converting to a "HIGH" signal in the conventional arrangement. Because the transistor used in the driving IC includes an amorphous silicon, having a slow response time in character, a need arises to guarantee the sufficient response time of the driving IC. Consequently, it is an important point that the signals used to drive the devices should be moderated according to the character of the materials making up the driving IC. If the driving ICs are composed of polysilicon, which has a faster response time, it is difficult to precisely control the driver IC.
Furthermore, according to the wave shape of the clock signals S1, S2 and S3, their "HIGH" states are overlapped with each other. The "HIGH" state of the S3 signal causes unpredicted influences to the shift signal. Therefore, most of the TFTs are simultaneously turned on when a scan line is selected. This results in the circuit of the driving IC having a high load.